Analyzing 20,000 open roles in the chip design job market • Erik Steiger

Why look at job postings

Everyone talks about AI automating chip design. Agents for RTL, agents for verification, “autonomous” flows at DAC. When I ask Chatty to research this matter, it usually reads the same ten marketing-heavy blog posts, so it isn’t a meaningful signal for this space. Job postings are a cheaper, more honest signal: a company only opens a req for work it is actually paying a human to do. So I pulled the open roles of the companies that design chips, build EDA tools, or build AI for chip design, and counted… or rather I let a sweep of Claude agents do all the work. So let’s get into it.

Sweet, sweeet data

We crawled 51 companies in total, mostly through their public career sites, all on a single day (30 Sep 2026). We can roughly cluster the companies into

EDA vendors: Synopsys, Cadence, Siemens EDA, Keysight EDA
chip majors: NVIDIA, AMD, Intel, Qualcomm, Arm, Broadcom, Marvell, MediaTek, Apple
hyperscaler silicon teams: Google, Amazon (Annapurna), Microsoft, Meta, OpenAI, Tesla
AI chip startups (US and Europe),
AI-for-chip-design startups,
European semis and research labs

Feel free to ask your AI what the differences are. All in all that adds up to 19,838 open postings, or 15,695 distinct roles, when counting the same title at the same company only once. I assigned each role a function (verification, RTL, physical design, …) based on its job title via some keyword rules (this would have actually been an awesome use case in using Jev but..oh well). This gives us ~6,800 roles as we dropped generic titles like “Senior Engineer”. Small caveats: obviously open postings measure hiring demand, not headcount; so big companies will usually have more open positions in general. The title-based tagging is only about 90% accurate and we completely ignored LinkedIn.

Where the open roles are

Open roles by function. Sales, marketing and field 17.0%, verification 13.5%, chip software 11.7%, RTL design 10.2%, architecture and modeling 9.7%, analog/mixed-signal 9.2%, DFT and test 6.7%, post-silicon 6.6%, physical design 5.6%, fab and process 5.1%, boards and systems 4.9%, CAD and methodology 4.8%, packaging and chiplets 4.4%, signoff 2.7%. — Share of 6,828 open roles that could be assigned a function from the job title.

Not surprising, but also not what we came for: the largest bucket is not engineering but sales, marketing and field roles (17%). After that the biggest engineering cluster are verification comes first (13.5%), then chip software (compilers, kernels, firmware) at 11.7% and RTL design (10.2%). The top two are close, and without the four EDA vendors, verification and chip software would be tied (798 vs 801 roles). Architecture and performance modeling (9.7%) is almost as big as RTL. It seems like a lot of people are paid to explore architectures before any RTL exists. Rumor has it that ML approaches are about to disrupt this, e.g., if one believes Ricursive Intelligence and their $4B valuation. Later stages of the chip pipeline are below 10% with DFT & test (6.7%) and post-silicon bring-up/validation (6.6%) each about as large as physical design (5.6%).

Who hires

Four panels comparing the function mix of chip majors, hyperscaler silicon teams, AI chip startups and AI-for-chip-design startups. The first three look similar, with verification and chip software at 16 to 22 percent. AI-for-chip-design startups are 55 percent RTL and have no signoff, DFT or post-silicon roles. — Function mix per group (chip-engineering roles only). Last panel: different axis, 29 roles.

Chip majors, hyperscaler silicon teams and AI chip startups look surprisingly alike:

verification 16–22%
chip software 18–21%
post-silicon ~10% everywhere

Looking at the details, chip majors hire far more analog/mixed-signal (12% vs 4%) probably because they ship SerDes, PHYs and power management, while hyperscalers and startups lean harder on verification and software. AI-for-chip-design startups are a different animal as only 29 of their 130 roles are chip-engineering roles at all; the rest are ML/software (75) and sales (22). Of those 29, more than half are RTL, and interestingly zero signoff, DFT/test or post-silicon roles. That is not surprising once you notice that almost all of them ship software, not silicon, so there is no need for signoff.

How much AI in job ads?

Grouped bar chart per EDA vendor. Mentions AI anywhere vs AI/ML is part of the job: Synopsys 47% vs 22%, Cadence 29% vs 27%, Siemens EDA 35% vs 32%, Keysight EDA 61% vs 64%. — Technical postings (R&D and application engineers), company boilerplate removed.

So the obvious question is “If AI is changing EDA, it should show up in the jobs of the people who build EDA”, right?

Of 1,124 technical postings at the four vendors, overall ~26% describe AI/ML as part of the job — tasks, skills or AI-assisted tools. I kinda thought it would be more, ngl. 38% mention AI somewhere, most likely in market framing (“IP for AI data centers”). Synopsys, the incumbent, has the widest gap: AI in 47% of postings, AI work in 22%. And only 4% of technical postings have AI or ML in the job title.

My read is that so far, AI has not changed what most engineers at the classical EDA vendors do day to day. That is not surprising, as adoption is always slow in enterprises. But it is also crazy to think of the potential when one sees how the capabilities of frontier models keep rising.

Is AI coming for verification jobs?

Bar chart of verification roles as a share of hardware-design roles per company. Publicly named agentic-EDA users: Tenstorrent 29%, NVIDIA 21%, Qualcomm 21%, AMD 21%, MediaTek 11%. Others range from Marvell 11% to MatX 33%. Pooled: 19.5% vs 19.4%. — Verification share of each company's hardware-design roles. Blue: publicly named users or evaluators of agentic EDA tools.

Agentic tools are pitched hardest at verification. If they substituted for engineers, the companies using them should be hiring fewer verification engineers. At least that’s the logic.

Publicly named users or evaluators:

NVIDIA, Qualcomm and Tenstorrent: Cadence ChipStack (Cadence, 2026)
AMD: Synopsys agentic workflows (Synopsys, 2026)
MediaTek: ChipAgents (TFN, 2026)

Looking at the result we see no difference. Verification is 19.5% of their hardware-design roles vs 19.4% at everyone else. The spread within each group (11% to 33%) is much larger than the gap between them. Of course the analysis is not perfect: “not publicly named” does not mean “not using”, as ChipAgents alone claims 120+ customers, and one snapshot can’t show a trend. So the verification job market is still big, including at the companies furthest ahead on agents.

We have AI-for-chip-design at home

Bar chart of open roles that apply AI or agents to a company's own design flow. NXP 12, NVIDIA 6, Infineon 6, ST 3, Qualcomm 3, then Tesla, OpenAI, Marvell, Bosch, Apple and AMD with 2 each, imec, Tenstorrent, MediaTek, Intel, IHP and Google with 1 each. European companies account for 25 of 48. — Open roles whose title applies AI/ML or agents to the company's own design, verification, implementation or test flow (EDA vendors excluded).

We find 48 open roles at 17 chip companies and labs whose title says they apply AI or agents to their own design flow. Some examples:

NXP: “Director AI/ML Driven ASIC Design and Implementation Automation”, with engineer, lead, principal and expert roles underneath
NVIDIA: “Applied Machine Learning Engineer, AI for VLSI Design”
ST: “Agentic AI Expert for Physical Design Automation”
Infineon: “Internship – Agentic AI for Hardware Test Automation”
OpenAI: “Research Engineer, AI for Chip Design”

While the EU gets a lot of bashing in AI, 25 of the 48 are at European companies: NXP (12), Infineon (6), ST (3), Bosch, imec, IHP. Because we detect this by matching titles, teams working under generic titles are missed. But notably, chip companies are not just waiting for EDA vendors or startups to ship agents.. some are staffing it themselves. As they should… but let’s wait and see how successful they are going to be.

What’s next?

To see a real trend, I would repeat the snapshot in ~3 months and look at what moves, especially verification at agent users. Chip companies are still hiring for DFT/test and post-silicon, but nobody in AI-for-chip-design is staffing them. More importantly, what about the European AI chip startups that post no jobs publicly? How close are they to silicon?

References

Cadence Design Systems (2026). Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification (press release, 10 Feb 2026). [link]
Synopsys (2026). Synopsys Advances Agentic AI Chip Design with AMD and Microsoft (press release, 27 Jul 2026). [link]
Tech Funding News (2026). Micron, MediaTek back ChipAgents as AI startup extends Series A to $134M on 6x ARR growth (29 Jul 2026). [link]